Design of a high-frequency second-order ΔΣ modulator

As the minimum feature size of VLSI technologies scales down, more of the signal processing tasks are performed in the digital domain, making the analog-to-digital converter (ADC) design critical. High speed designs can be achieved by using oversampling ADC structures. At high sampling rates, the resolution appears to be limited by amplifier settling requirements. Design techniques to improve the ADC performance are presented. The proposed modulator structure uses the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operates even with low DC gain amplifiers.