The VHDL based design of the MIDA MPEG1 audio decoder

Author

Finotello, Andrea ; Paolini, Maurizio

Author_Institution

CSELT, Torino, Italy

fYear

1995

fDate

18-22 Sep 1995

Firstpage

579

Lastpage

584

Abstract

This paper describes the features and design methodology of MIDA, an MPEGI integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL descriptions, and has been implemented using a cell based approach and a 0.7 μm, 2 metal layers CMOS technology. The die area is 95 mm². Synthesis tools have also been used for automatic insertion of test structures and automatic test pattern generation

Keywords

CMOS integrated circuits; decoding; hardware description languages; synchronisation; 0.7 micron; 2 metal layers CMOS technology; MIDA MPEG1 audio decoder; VHDL based design; VHDL descriptions; automatic insertion; automatic synthesis; automatic test pattern generation; cell based approach; die area; test structures; Automatic testing; CMOS technology; Circuit synthesis; Circuit testing; Decoding; Design methodology; Frequency synchronization; Phase change materials; Registers; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Conference_Location

Brighton

Print_ISBN

0-8186-7156-4

Type

conf

DOI

10.1109/EURDAC.1995.527464

Filename

527464

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3545516