DocumentCode :
3545935
Title :
Low-power design methodology for DSP systems using multirate approach
Author :
Wu, An-Yeu ; Liu, K. J Ray ; Zhan, Zhongying ; Nakajima, Kazuo ; Raghupathy, Arun
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Volume :
4
fYear :
1996
fDate :
12-15 May 1996
Firstpage :
292
Abstract :
We present a low-power design methodology based on the multirate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic way to design low-power DSP systems at the algorithmic/architectural level. The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different architectures: One is the normal pipelined design and the other is the multirate design with downsampling rate equal to two. The experimental results show that the multirate FIR chip consumes only 21% power of the normal FIR chip given the same data throughput rate
Keywords :
FIR filters; VLSI; digital signal processing chips; integrated circuit design; DSP system; FIR VLSI chip; algorithm; architecture; data rate; downsampling rate; low-power design; multirate design; pipelined design; throughput rate; Algorithm design and analysis; Design methodology; Digital signal processing; Digital signal processing chips; Energy consumption; Finite impulse response filter; Throughput; Transfer functions; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.541959
Filename :
541959
Link To Document :
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