HDL generation from parameterized schematic design system

This paper presents an HDL generation method for generating synthesizable Verilog and VHDL models for DSP designs captured using a block-based schematic system. The schematic library consists of parameterized blocks that model various algorithmic functions. A schematic description of a design is first mapped to an HDL (Hardware Description Language) description, which is then synthesized using an RTL (Register-Transfer Level) or a behavioral synthesis tool. The HDL description generated by this method is optimized, easy-to-read and suited for RTL and behavioral synthesis tools. The synthesis results presented for some examples demonstrate the advantages of this technique