Research on metastability based on FPGA

Multi-clock is commonly used in complex systems. So if synchronous signals in one clock domain are transferred to another clock domain, they will become asynchronous signals. Asynchronous signals will cause metastable state, which will lead to unpredictable results. How metastabilities led to errors in a system is described first. Then a simulation of RS flip flop using pspice is to show the detail procedure of metastability. To demonstrate how often metastabilities will happen, a FPGA based experimentation is realized by changing the internal layout of flip flop manually, which changes the propagation delay between them.