Data dependent precharging dynamic chain architecture for low power end high speed adders

Author

Paik, Woo-Hyun ; Hwang, In-Chul ; Kim, Jae- Wan ; Kim, Soo- Won

Author_Institution

Innovation Center, LG Corp. Inst. of Technol., Seoul, South Korea

fYear

1997

fDate

7-10 Sep 1997

Firstpage

173

Lastpage

177

Abstract

This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the `precharge´ mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation

Keywords

adders; 270 MHz; 3.3 V; 64 bit; DDP dynamic chain architecture; data dependent precharging; low power high speed adder; simulation; spurious transition; Adders; Application specific integrated circuits; Degradation; Digital filters; Digital signal processing; Digital systems; Electronic mail; Energy consumption; Power generation; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.617000

Filename

617000

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3545998