Synthesize pass transistor logic gate by using free binary decision diagram

Author

Tachibana, Masayoshi

Author_Institution

Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan

fYear

1997

fDate

7-10 Sep 1997

Firstpage

201

Lastpage

205

Abstract

In this paper, a heuristic algorithm for free BDD node minimization is presented. This algorithm is designed to minimize small size FBDDs with application to synthesize pass transistor logic gate families. Experimental results based on 169 single output functions from MCNC benchmark two-level logic examples indicate 22 to 24% reduction of node count compared with initial ROBDD. Also, experimental results based on HWB functions (N=3-16) indicate node count reduced to 30 to 40% larger than the theoretical limit

Keywords

Boolean functions; circuit optimisation; data structures; logic CAD; logic gates; DCVS; HWB functions; MCNC benchmark two-level logic; free binary decision diagram; heuristic algorithm; node count; node minimization; pass transistor logic gate; single output functions; Binary decision diagrams; Boolean functions; Data structures; Driver circuits; Logic circuits; Logic functions; Logic gates; Logic testing; Minimization; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.617005

Filename

617005

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3546120