• DocumentCode
    3546198
  • Title

    A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators

  • Author

    Lao, Chon-In ; U, Seng-Pan ; Martins, R.P.

  • Author_Institution
    Analog & Mixed-Signal VLSI Lab., Univ. of Macau, Macao, China
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    3095
  • Abstract
    This paper presents a novel architecture for a high-order cascade oversampling modulator: semi-MASH based on the application of stage feedback within each stage and using appropriate error cancellation logic to spread the noise transfer function (NTF) zero to extend the signal-to-quantization noise ratio (SNQR). Moreover, minimum-noise-shaping-per-stage keeps 0dB overload region regardless of the stage number. An 8×OSR 5th order 1.5-bit semi-MASH design (1+1-1+1-1mb) is presented as an example achieving 81 dB peak SNQR and 88 dB SFDR. More than 14 dB SNQR and 12 dB SFDR are gained by spreading the NTF zero. Behavioral simulations with MATLAB and SIMULINK demonstrate the good performance of the proposed architecture.
  • Keywords
    cascade networks; circuit feedback; poles and zeros; sigma-delta modulation; signal sampling; transfer functions; NTF zero; error cancellation logic; high-order cascade sigma-delta modulators; noise transfer function zero; oversampling modulator; performance; semi-MASH sub-stage; signal-to-quantization noise ratio; stage feedback; Bandwidth; Delta-sigma modulation; Energy consumption; Feedback; Logic; Multi-stage noise shaping; Noise cancellation; Noise shaping; Signal to noise ratio; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
  • Print_ISBN
    0-7803-8834-8
  • Type

    conf

  • DOI
    10.1109/ISCAS.2005.1465282
  • Filename
    1465282