A low-power, 32-bit RISC processor with signal processing capability and its multiply-adder

Author

Nadehara, Kouhei ; Hayashida, Miwako ; Kuroda, Ichiro

Author_Institution

Inf. Technol. Res. Lab., NEC Corp., Kawasaki, Japan

fYear

1995

fDate

16-18 Oct 1995

Firstpage

51

Lastpage

60

Abstract

A 500 mW, 100 MHz, 32-bit RISC microprocessor, designed for software signal processing is described. Its signal processing oriented instruction set includes fast integer/fixed-point multiply/multiply-accumulate instructions, minimum/maximum instructions and conditional branch instructions with prediction etc. The processor integrates a 200 MHz, 32-bit compact multiply-adder with a parallel overflow detector in its pipeline to achieve peak signal processing performance of 200 MOPS. Through the employment of this fast multiply-adder, this microprocessor is able to obtain higher signal processing performance than other RISC processors

Keywords

adders; digital signal processing chips; instruction sets; microprocessor chips; multiplying circuits; reduced instruction set computing; 100 MHz; 32 bit; 500 mW; conditional branch instructions; integer/fixed-point multiply/multiply-accumulate instructions; low-power RISC processor; microprocessor; minimum/maximum instructions; multiply-adder; parallel overflow detector; pipeline; prediction; signal processing; Central Processing Unit; Digital signal processing; Microcomputers; Microprocessors; National electric code; Pipelines; Reduced instruction set computing; Signal processing; User interfaces; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]

Conference_Location

Sakai

Print_ISBN

0-7803-2612-1

Type

conf

DOI

10.1109/VLSISP.1995.527476

Filename

527476