A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing

A novel architecture is proposed for a low-power reconfigurable unsigned multiplier with one level of recursion. Compared with the conventional scheme for n×n-b unsigned multiplication, which employs four n/2×n/2 non-additive multiply modules (NMMs), the proposed architecture uses two n/2×n/2-b NMMs and one (n/2+1)×(n/2+1) NMM, thereby eliminating one n/2×n/b-2 NMM. This is done by developing a new principle for NMM-based multiplication, and by developing a novel Wallace tree capable of dealing with partial products of both positive weight and negative weight. The incurred overhead includes two n/2-b carry propagation adders. Simulation results for a 64×64-b unsigned reconfigurable multiplier in TSMC 0.35-μm digital CMOS technology show 20% reduction in transistor count with only 7% increase in multiplication time.