A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms

The paper proposes a novel multi-layer AMBA high-speed bus (AHB) infrastructure designed to sustain a clock frequency of more than 2 GHz, which remarkably provides up to 4 giga data transfers per second of throughput. The interconnect matrix is achieved through a collection of high-performance bridges that serialize transfers toward a high-throughput shared-memory. As a result, we guarantee a maximum of one cycle communication latency to sixteen 125 MHz processors connected to our infrastructure. The proposed solution has been designed and verified with Cadence tools using a 0.18 μm CMOS technology.