Low-cost CMOS compatible sintered porous silicon technique for microbolometer manufacturing

This paper reports about the development of a low-cost, CMOS compatible process technology to create thermally insulated pixel regions for integrated microbolometers. The enabling technology is based on a modified sintered porous silicon (sPS) technique. An array of 280 × 240 thermally isolated pixels with lateral dimensions of 30 × 30 μm² and epitaxial silicon (Si) thickness down to 500 nm is presented. In the final design the pixel is suspended by silicon dioxide (SiO₂) arms. The design and fabrication process is described and mechanical deformation properties subtracted from profilometer images are presented.