DocumentCode
3546508
Title
A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis
Author
Hegedus, Ákos ; Maggio, Gian Mario ; Kocarev, Ljupco
Author_Institution
Inst. for Nonlinear Sci., Univ. of California, San Diego, La Jolla,, CA, USA
fYear
2005
fDate
23-26 May 2005
Firstpage
3375
Abstract
NoC (network-on-chip) is an emerging paradigm that copes with the increasing complexity and communication requirements of current SoCs (system-on-chip). We present an ns-2 (network simulator) simulation environment for NoC traffic analysis. Namely, the NoC model is illustrated in detail and simulation results are reported. One-dimensional chaotic maps are used for generating long-range dependent traffic.
Keywords
chaos; circuit simulation; integrated circuit design; integrated circuit interconnections; system-on-chip; telecommunication computing; telecommunication traffic; SoC communication requirements; chaotic maps; long-range dependent traffic; network simulator; network-on-chip traffic analysis; ns-2 simulator; Analytical models; Chaos; Circuit simulation; Clocks; Computational modeling; Integrated circuit technology; Network-on-a-chip; System-on-a-chip; Telecommunication traffic; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465352
Filename
1465352
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