Title :
Synthesis of building blocks for low-power stochastic pulse coded systems
Author :
Naess, S. ; Lande, Tor Sverre
Author_Institution :
Dept. of Inf., Oslo Univ., Norway
Abstract :
This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block
Keywords :
analogue integrated circuits; analogue processing circuits; application specific integrated circuits; circuit CAD; integrated circuit design; integrating circuits; building blocks synthesis; design properties; device-level synthesis; low-power stochastic pulse coded systems; pulse integrator; Computer vision; Fuzzy systems; Geometry; Informatics; Parallel processing; Pattern recognition; Signal representations; Signal synthesis; Stochastic systems; Upper bound;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.617015
