Power-driven NoC design optimization with low swing interconnect

As a solution for interconnection problems on System on Chip (SoC), Networks on Chips (NoCs) are popularly used in large integrated Circuits (ICs) design. However, power consumed by on chip communications takes significant part of the overall power budget as the number of cores on a chip increases. To tackle the problem, the low swing interconnects can be integrated into NoCs to save the power consumption with high performance. Most low swing techniques are used to optimize the performance. In this paper, we propose a power-driven optimization method to further decrease the energy consumption under delay constraint. We construct a power-delay optimization model to evaluate the repeater size and inter-repeater interconnect length for a given global low swing interconnect based on which the energy consumption could be reduced with a delay increase. Hence the proposed model is used in our power-driven method to optimize the energy consumption for NoC designs. The simulation results show that the energy consumption of CDLSI based interconnects can be further reduced by nearly 36% compared to the conventional delay optimization method while the latency is almost the same with the delay optimal conventional full swing interconnects.