A 3-D parasitic extraction flow for the modeling and timing analysis of FinFET structures

The FinFET technology is considered as the best candidate to extend the CMOS technology down to 10 nm. In this paper, a three-dimensional (3-D) parasitic extraction flow is proposed for modeling and timing analysis of the FinFET based circuits. The flow fully considers the 3-D geometry of the FinFET and employs accurate field solvers for extracting resistances and capacitances. Thus, it accurately captures the prominent coupling effect between the FinFET and lower-layer interconnects. With the input of industry-standard layout data, the flow outputs the SPICE RC netlist for timing analysis. Numerical experiments on FinFET structures and other digital design demonstrate the efficiency and accuracy of the proposed extraction flow. This work provides an efficient supplement to the exiting parasitic extraction methodology for the FinFET technology.