Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Author

Liang, Xiaoyao ; Athalye, Akshay ; Hong, Sangjin

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

3511

Abstract

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

Keywords

buffer circuits; data flow computing; digital signal processing chips; integrated circuit design; pipeline processing; real-time systems; reconfigurable architectures; FPGA; block level pipelining; buffers; data centric applications; dynamic coarse grain dataflow reconfiguration technique; heterogenous processing elements; real-time signal processing applications; real-time systems design; reconfigurable interconnects; reconfigurable platform design methodology; runtime reconfiguration overhead; throughput; Computer architecture; Design methodology; Digital signal processing; Integrated circuit interconnections; Parallel processing; Pipeline processing; Real time systems; Reconfigurable architectures; Switches; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465386

Filename

1465386