Litho-driven layouts for reducing performance variability

Gate length variability is the dominant cause of performance variability in nanometer IC technologies. In this work, layout design techniques for reducing gate length variability are presented. It involves making choices in the layout design that improve the dimensional control of the lithographic process. By relaxing the minimum pitch and by reducing the proximity variations for the gate lines, the litho-process is improved. Litho-simulations and statistical circuit simulations are done on various circuit layouts to estimate the resulting improvement in the gate length spreads and corresponding delay spreads. The litho-driven layouts show a factor of two improvement in the delay spread at the cost of small area and speed penalty.