Timing error correction techniques for voltage-scalable on-chip memories

We describe new DVS-capable SRAM circuit techniques and sensing schemes that enable timing error correction for memories. The sensing scheme and circuit techniques enable aggressive voltage scaling and eliminate conventional design margins considering (i) inter- and intra-die process variations, (ii) local supply voltage variations, and (iii) temperature fluctuations. The proposed techniques enable the exploitation of address and data-dependent memory access delays, allowing additional voltage scaling within a given error recovery energy budget. Applications allowing a fraction of latent operations enable voltage-scaling below a critical voltage. Below this critical voltage point, occasional temperature, voltage and process variations induce timing errors in critical paths which are detected and corrected by the proposed circuits. Simulation results indicate that the techniques enable aggressive supply voltage-scaling to obtain power savings from 12 to 35%.