ASIC design of fast IP-lookup for next generation IP router

One of the prime designs for the next generation IP routers is the IP-lookup mechanism. The IP lookup has become a major performance bottleneck for the routers. In this paper, we propose a complete hardware architecture which includes searching, updating, inserting, and deleting functions. A simple hash hardware design is used to reduce the lookup time, and a CAM is also used to solve the collision problems effectively. The ASIC includes search unit, memory controller, 1M-byte cache and 3.18 Kbytes CAM for a 32000 entries routing table. The searching, updating and deleting functions only need 1 cycle and it is 96.88% to chance to hit the correct next hop in the first cycle.