• DocumentCode
    3546859
  • Title

    Quantifying the performance impacts of using local memory for many-core processors

  • Author

    Jianbin Fang ; Sips, Henk ; Varbanescu, Ana Lucia

  • Author_Institution
    Delft Univ. of Technol., Delft, Netherlands
  • fYear
    2013
  • fDate
    7-7 Sept. 2013
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    Due to the increasing complexity of multi/many-core architectures (with their mix of caches and scratch-pad memories) and applications (with different memory access patterns), the performance of many workloads becomes increasingly variable. In this work, we address one of the main causes for this performance variability: the efficiency of the memory system. Specifically, based on an empirical evaluation driven by memory access patterns, we qualify and partially quantify the performance impact of using local memory in multi/many-core processors. To do so, we systematically describe memory access patterns (MAPs) in an application-agnostic manner. Next, for each identified MAP, we use OpenCL (for portability reasons) to generate two microbenchmarks: a “naive” version (without local memory) and “an optimized” version (using local memory). We further evaluate both of them on typically used multi-core and many-core platforms, and we log their performance. What we eventually obtain is a local memory performance database, indexed by various MAPs and platforms. To show how our database can be used to provide information on local memory usage, we demonstrate a scenario for performance prediction: given an application, its MAPs, and a platform, a query in the database can indicate the performance impact of using local memory for the given application. This indication can be used to either avoid the hassle of implementing optimizations with too little gain or, alternatively, give a rough prediction of the performance gain.
  • Keywords
    cache storage; parallel architectures; performance evaluation; MAPs; OpenCL; application-agnostic manner; caches; local memory performance database; many-core architecture complexity; many-core processors; memory access patterns; microbenchmarks; multicore architecture complexity; performance gain prediction; performance impacts; performance prediction; performance variability; scratch-pad memories; Instruction sets; Local Memory; Memory Access Pattern; Micro-Benchmarking; OpenCL; Performance Prediction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multi-/Many-core Computing Systems (MuCoCoS), 2013 IEEE 6th International Workshop on
  • Conference_Location
    Edinburgh
  • Type

    conf

  • DOI
    10.1109/MuCoCoS.2013.6633601
  • Filename
    6633601