A low-power pipeline ADC using a novel MDAC without opamp and a foreground calibration technique

A 10 bit, 80MS/s pipeline ADC used for communication applications is presented in this paper. In order to meet the requirement of low power and high SNR, a novel first stage with S/H function replaces the traditional S/H front-end. Meanwhile, taken trade-off between high performance and low power into consideration, in the last several stages, MDAC involved closed-loop with opamp is cancelled, a novel capacitive charge pump with foreground calibration is proposed for MADC. Implemented in a 0.18μm CMOS process, SNR and SFDR are 57.52dB and 67.68dB, respectively, when a 1MS/s sinusoid signal inputs to the ADC at 80MS/s sampling rate. Total power consumption is only 8.3mW from 1.8V power supply.