Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach

Author

Seo, Yoon-Deuk ; Nam, Dongkyung ; Yoon, Byoung-Jin ; Choi, Il-Hyun ; Kim, Beomsup

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

1997

fDate

7-10 Sep 1997

Firstpage

316

Lastpage

320

Abstract

This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 μm DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 μA with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm/°C at temperatures ranging from 0°C to 100°C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits

Keywords

CMOS memory circuits; DRAM chips; circuit optimisation; genetic algorithms; integrated circuit design; reference circuits; 0 to 100 C; 0.5 micron; 2.8 to 4 V; 8 muA; DRAM; EP; MOS PTAT; MOS transistor; circuit design; evolutionary programming; low-power CMOS on-chip voltage reference; optimization; proportional to the absolute temperature; temperature coefficient; threshold voltage; CMOS process; Current measurement; MOSFETs; Power generation; Power supplies; Random access memory; Temperature distribution; Temperature measurement; Temperature sensors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.617029

Filename

617029