Ultra low voltage design considerations of SOI SRAM memory cells

This paper introduces a systematic design methodology dedicated to partially depleted SOI (PD-SOI) SRAM memory cells. We have adapted the conventional design methods in order to take into account the secondary effects that are related to the PD-SOI floating body transistor. The method has been applied both to a conventional 6-transistor SRAM cell and a 4-transistor self-refresh cell we have developed. Comparisons based on simulations using a 130 nm PD-SOI technology are presented.