Power-aware slack distribution for hierarchical VLSI design

Hierarchical design plays an important role in microprocessor and ASIC domains where design complexity limits design productivity and tool capacity. Slack distribution, which assigns arrival times and required arrival times at hierarchical boundaries, is a key component in resolving timing issues. In this paper, we present a new slack distribution methodology targeting power minimization. The approach is formulated as a nonlinear optimization problem, which can be solved very efficiently. Experiments with example designs show that up to 14% power can be saved with the proposed methodology.