Fast parameters optimization of an iterative decoder using a configurable hardware accelerator

In this paper, a novel methodology for parameters optimization of an iterative decoder architecture is proposed. This approach uses an on-chip configurable implementation of the architecture to accelerate the optimization process. A new class of iterative threshold decoder has been integrated on a field programmable gate array together with a prototype of a communication system. The decoding performance of this iterative threshold decoder is somewhat dependent upon weight values in the decoding process. This new optimization approach using a hardware implementation of the architecture allows us to quickly find the most appropriate set of weighing factors. The accelerated hardware-software optimization process yields experimental results after 1.97 hours of computation instead of 321.16 days with a software decoder version, resulting in an optimization acceleration factor of 3908.