• DocumentCode
    3547173
  • Title

    A VLSI model of the bat dorsal nucleus of the lateral lemniscus for azimuthal echolocation

  • Author

    Shi, Rock Z. ; Horiuchi, Timothy K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    4217
  • Abstract
    The dorsal nucleus of the lateral lemniscus (DNLL) is a distinct group of auditory cells that play a strategic role in azimuthal echolocation in the bat. Dominated by EI-type cells that receive excitation from the contralateral ear and inhibition from the ipsilateral ear, the DNLL processes interaural level difference (ILD) information by integrating inputs from lower brainstem areas and projecting its outputs to the midbrain. In this paper, we propose a two layer recurrent spiking neural network model that simulates ILD processing by the DNLL, and present a VLSI implementation using the address-event representation (AER) protocol. We demonstrate, using this neuromorphic VLSI-based hardware system, that long-lasting inhibition in the DNLL can alter its spatial selectivity to multiple sounds (objects).
  • Keywords
    VLSI; bioacoustics; neural chips; recurrent neural nets; sonar signal processing; sonar tracking; AER protocol; DNLL auditory cells; DNLL long-lasting inhibition; EI-type cells; ILD processing; VLSI implementation; address-event representation; bat azimuthal echolocation; bat dorsal nucleus VLSI model; bat lateral lemniscus dorsal nucleus; contralateral ear excitation; interaural level difference processing; ipsilateral ear inhibition; lower brainstem area inputs; midbrain; multiple objects spatial selectivity; multiple sounds spatial selectivity; neuromorphic hardware system; sonar echoes; two layer recurrent spiking neural network; Biological system modeling; Cognitive science; Ear; Educational institutions; Neural networks; Neuromorphics; Neurons; Neuroscience; Recurrent neural networks; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
  • Print_ISBN
    0-7803-8834-8
  • Type

    conf

  • DOI
    10.1109/ISCAS.2005.1465561
  • Filename
    1465561