• DocumentCode
    3547225
  • Title

    Using voltage and temperature adders to account for variations in operating conditions during digital timing simulation

  • Author

    Hayes, Jerry D. ; White, David B.

  • Author_Institution
    Microelectron. Div., IBM Corp., Essex Junction, VT, USA
  • fYear
    1997
  • fDate
    7-10 Sep 1997
  • Firstpage
    348
  • Lastpage
    351
  • Abstract
    Rather than applying the historical approach of using voltage and temperature multipliers to scale timing performance in digital simulators, adders are used to model the change in performance due to variations in operating conditions (voltage and temperature). The adders are treated as functions of input transition rate (Tx) and output load capacitance (Cload) and greatly improve the absolute accuracy of the timing simulator as compared to using multipliers. A methodology for predicting the sensitivity of timing performance to variations in voltage and temperature is presented
  • Keywords
    adders; application specific integrated circuits; capacitance; circuit analysis computing; integrated circuit design; timing; ASIC; IC design; adders; circuit simulation; digital timing simulation; input transition rate; operating conditions; output load capacitance; sensitivity; Accuracy; Adders; Calibration; Circuit simulation; Delay; Equations; Predictive models; Temperature; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
  • Conference_Location
    Portland, OR
  • ISSN
    1063-0988
  • Print_ISBN
    0-7803-4283-6
  • Type

    conf

  • DOI
    10.1109/ASIC.1997.617035
  • Filename
    617035