Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder

The EBCOT (embedded block coding with optimised truncation) block coder is one of the main resource intensive components of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder system. Concurrent symbol processing (CSP) is a promising technique to increase the throughput of the block coder at significantly less increase in the hardware cost. We present an efficient VLSI architecture for the buffer required to realize a CSP capable block coder for the JPEG2000 encoder. Our contributions include the study of the contexts-generation pattern of the natural images for an optimal selection of buffer parameters, viz., buffer length and context-accepting capacity, and the design of a low cost VLSI architecture for the buffer. The architecture is implemented using Altera APEX20KE FPGA and experimental results show that the optimal selection of the buffer parameters results in savings of 76% in the hardware cost with a minimal reduction of 2% in the overall block coder throughput.