Title :
A general method to double the cycle simulation speed
Author_Institution :
IBM Deutschland GmbH, Boeblingen, Germany
Abstract :
Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today´s highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed
Keywords :
circuit analysis computing; flip-flops; hardware description languages; logic CAD; RT level; cycle simulation speed; high speed simulation; logic simulation; master/slave latch pairs; optimized hardware designs; single latch models; Clocks; Design optimization; Formal verification; Hardware; Logic arrays; Logic design; Logic functions; Master-slave; Wire; Workstations;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.617037
