DocumentCode
3547289
Title
A general method to double the cycle simulation speed
Author
Gerst, Harald
Author_Institution
IBM Deutschland GmbH, Boeblingen, Germany
fYear
1997
fDate
7-10 Sep 1997
Firstpage
356
Lastpage
359
Abstract
Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today´s highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed
Keywords
circuit analysis computing; flip-flops; hardware description languages; logic CAD; RT level; cycle simulation speed; high speed simulation; logic simulation; master/slave latch pairs; optimized hardware designs; single latch models; Clocks; Design optimization; Formal verification; Hardware; Logic arrays; Logic design; Logic functions; Master-slave; Wire; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location
Portland, OR
ISSN
1063-0988
Print_ISBN
0-7803-4283-6
Type
conf
DOI
10.1109/ASIC.1997.617037
Filename
617037
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