Novel digital signal processing unit for Ethernet receiver

The paper proposes a novel digital signal processing (DSP) unit for an Ethernet receiver. The proposed DSP unit consists of a programmable gain amplifier (PGA), a timing recovery, a new adaptive equalizer, and a proposed baseline wander (BLW) compensator. The proposed adaptive equalizer uses 2^-7 as the optimum step size, i.e., μ. Since the optimum step size is a multiple of 2, the equalizer can eliminate multipliers. Hence, the proposed equalizer has small area and consumes low power. In addition, the proposed BLW compensator implemented in a digital domain uses four symbols, including the present symbol, and can remove BLW at the channel having large BLW. To verify the performance, we simulate the proposed DSP unit using the SPW^™ tool. The implemented DSP unit using the 0.18 μm SEC cell library operates at 142.7 MHz and consists of 128,528 gates. The measured BER is less than 10^-10 when the transmitted data is received up to 150 m.