A scalable pipelined complex valued matrix inversion architecture

This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R^-1 with Q. We show that traditional triangular array architectures employing O(n²) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system.