A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher

A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to previous ones, supports both encryption and decryption processes. It is based on the unrolling of the MISTY1 rounds in a 75-stage pipeline. Furthermore, the implementation of the proposed architecture in specific FPGA devices utilizes the embedded RAM blocks of those devices. A throughput of up to 12.6 Gbit/s can be achieved at a clock frequency of 168 MHz. So, the proposed architecture is suitable for applications with high throughput requirements, like in contemporary and future wireless communication standards.