Title :
Design techniques for low-power cascaded CML gates
Author :
Alioto, Massimo ; Palumbo, Gaetano
Author_Institution :
Dipt. di Ingegneria dell´´Informazione, Siena Univ., Italy
Abstract :
In this paper, design techniques for cascaded current mode logic (CML) gates are proposed. Criteria to size each gate bias current in a cascade of CML gates are derived in practical design cases, i.e. when a high speed or a low power consumption is targeted. The analytical results are simple. Design examples based on a 20 GHz bipolar process are presented to clarify and validate the procedure.
Keywords :
bipolar logic circuits; cascade networks; current-mode logic; logic gates; low-power electronics; power consumption; 20 GHz; bipolar process; gate bias current; low-power cascaded CML gates; power consumption; Application specific integrated circuits; Artificial satellites; Bipolar integrated circuits; Delay; Energy consumption; High speed optical techniques; Integrated optics; Logic circuits; Optical fiber communication; Photonic integrated circuits;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465678
