More than two orders of magnitude leakage current reduction in look-up table for FPGAs

A leakage current reduction scheme based on ZSCCMOS (zigzag super cutoff CMOS) is proposed for a LUT (look-up table) using input forcing and an overdriven power gate. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times shorter than that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads are 15% and 8%, respectively.