Title :
More than two orders of magnitude leakage current reduction in look-up table for FPGAs
Author :
Tran, Canh Q. ; Kawaguchi, Hiroshi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Japan
Abstract :
A leakage current reduction scheme based on ZSCCMOS (zigzag super cutoff CMOS) is proposed for a LUT (look-up table) using input forcing and an overdriven power gate. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times shorter than that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads are 15% and 8%, respectively.
Keywords :
CMOS logic circuits; field programmable gate arrays; leakage currents; low-power electronics; table lookup; FPGA; LUT wake-up time reduction; ZSCCMOS; input forcing; leakage current reduction; look-up table; overdriven power gates; zigzag super cutoff CMOS; CMOS technology; Clocks; Cost function; Delay; Field programmable gate arrays; Leakage current; Multiplexing; Random access memory; Table lookup; Time to market;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465682
