Title :
An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications]
Author_Institution :
Electron. Dept., Kent Univ., Canterbury, UK
Abstract :
This paper presents an evaluation of an algorithm for performing the forward and inverse discrete cosine transforms (DCT) on digital images using a hybrid-logarithmic number system (hybrid-LNS) instead of linear binary arithmetic. The algorithm has been simulated using Matlab® where the accuracy of the fractional part of the logarithm has been limited to 8 bits and has been calculated using just 4, 6 or 8 binary address bits of the linear input data. The results show that it is possible to use this hybrid-LNS architecture to build multiplierless DCT and IDCT transforms having only a minimal reduction in image quality. The algorithm is suitable for implementation on existing mid-range FPGA technologies where there are limitations on the size of on-chip memory and high-speed computing elements.
Keywords :
digital arithmetic; discrete cosine transforms; field programmable gate arrays; image coding; 8 bit; FPGA; hybrid-LNS; hybrid-logarithmic number system; image compression; image quality; inverse discrete cosine transforms; logarithm fractional part accuracy; multiplierless DCT; multiplierless IDCT; Arithmetic; Computer architecture; Digital images; Discrete cosine transforms; Discrete transforms; Image coding; Nonlinear equations; Performance evaluation; Table lookup; Transform coding;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465722