A low-power distributed wide-band LNA in 0.18 μm CMOS

Author

Arekapudi, Srikanth ; Iroaga, Echere ; Murmann, Boris

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

5055

Abstract

The implementation of low noise amplifier (LNA) front-ends is one of the challenging aspects in emerging ultra wide-band (UWB) radio frequency (RF) systems. In this paper, we propose a figure of merit (FOM) that captures the tradeoffs among linearity, noise figure (NF), power dissipation and utilization of raw technology speed. Different distributed amplifier (DA) architectures with a 10 dB pass band gain and 10 GHz bandwidth are designed and simulated in 0.18 μm CMOS technology. The power consumption is reduced by using a Z₀ higher than the conventional 50 Ω, resulting in a four-section cascode DA that dissipates 12 mW from a single 1.8-V power supply. The NF and the output-referred 1-dB compression point at 5 GHz are 3.15 and 2.7 dBm.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; distributed amplifiers; low-power electronics; wideband amplifiers; 0.18 micron; 1.8 V; 10 GHz; 10 dB; 12 mW; 3.15 dB; 5 GHz; CMOS; UWB systems; distributed LNA; figure of merit; four-section cascode DA; low noise amplifier front-ends; low-power LNA; wide-band LNA; Broadband amplifiers; CMOS technology; Linearity; Low-noise amplifiers; Noise figure; Noise measurement; Power dissipation; Radio frequency; Radiofrequency amplifiers; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465770

Filename

1465770