Title :
A 80 μW/frame 104×128 CMOS imager front end for JPEG compression
Author :
Bandyopadhyay, Abhishek ; Lee, Jungwon ; Robucci, Ryan ; Hasler, Paul
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
We present a programmable 80 μW/frame (3.3 V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc). Floating-gate technology is used for on-chip kernel storage and also for performing low-power current-mode matrix multiplications. We demonstrate this IC as a front-end for JPEG compression and compare the performance of this imager to fully digital approaches.
Keywords :
CMOS analogue integrated circuits; CMOS image sensors; analogue processing circuits; current-mode circuits; image processing; integrated circuit design; low-power electronics; matrix multiplication; transforms; 104 pixel; 128 pixel; 13312 pixel; 3.3 V; CMOS imager; DCT; Haar transform; JPEG compression front end; analog image processor; block matrix transforms; floating-gate technology; low-power current-mode matrix multiplication; on-chip kernel storage; single-chip architecture; CMOS technology; Circuit testing; Computer architecture; Digital control; Image coding; Kernel; Parallel programming; Pixel; Sensor arrays; Transform coding;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465836
