A background correction technique for timing errors in time-interleaved analog-to-digital converters

Author

Iroaga, Echere ; Murmann, Boris ; Nathawad, Lalitkumar

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

5557

Abstract

A background correction scheme for timing mismatch in time-interleaved analog-to-digital converters (ADCs) is presented. The architecture is based on the use of an extra ADC channel and an input ramp signal to estimate the timing errors, and digital interpolation to correct the output digital codes. Simulated results demonstrate a 35 dB improvement in SFDR (spurious free dynamic range) and a 20 dB improvement in SNDR (signal-to-noise-and-distortion ratio) for a 10-bit converter with an over-sampling ratio greater than 2 times.

Keywords

analogue-digital conversion; interpolation; network synthesis; parameter estimation; timing; ADC channel; background correction technique; digital codes; digital interpolation; input ramp signal; over-sampling ratio; signal-to-noise-and-distortion ratio; spurious free dynamic range; time-interleaved analog-to-digital converters; timing error estimation; timing mismatch; Analog-digital conversion; Clocks; Degradation; Error correction; Error correction codes; Frequency; Interpolation; Jitter; Sampling methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465896

Filename

1465896