A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90 nm digital CMOS process

A multirate multibit sigma delta modulator structure is used for low power A/D converter design for wireless applications. New integrator structures and a dedicated timing scheme are proposed for a very low power implementation. A dual-mode second order multirate multibit sigma delta modulator targeting GSM/WCDMA applications is designed. In Spice simulations, the prototype design achieves 71.4 dB peak signal-to-noise+distortion (SNDR) in the 200 kHz GSM band and dissipates 1.1 mA of total current from a 1.5 V supply. This dual-mode design also achieves 45.7 dB SNDR in the 1.94 MHz WCDMA band with 1.9 mA of total current consumption.