Time-interleaved multirate sigma-delta modulators

A new strategy for the implementation of multirate sigma-delta modulators (SDM) is proposed in this paper. In multirate SDM, the first integrator is clocked at a rate lower than the rest of the integrators in the forward path. In the new architecture, each integrator clocked at the high rate is replaced by two parallel integrators operating in interleaving mode and clocked at the same low rate as the first one. The new architecture has several nice features. Firstly, all integrators operate at the same low rate, which simplifies the clock generation circuit. Secondly, the delayed cross-paths in time-interleaved (TI) SDM, which are difficult to implement, are not present in the proposed architecture. Thirdly, the high-rate sample and hold (S and H) circuit at the input of TI-SDM is replaced by a low-rate one in the proposed modulator. Finally, the first integrator is clocked at low rate and is implemented as a single-path module. Accordingly, the modulator is simplified in silicon area and complexity. Furthermore, the architecture is very robust to mismatch between paths.