Title :
Design of MOS current mode logic gates - computing the limits of voltage swing and bias current
Author :
Caruso, Giuseppe
Author_Institution :
Dipt. di Ingegneria Elettrica, Palermo Univ., Italy
Abstract :
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
Keywords :
MOS logic circuits; current-mode logic; logic design; logic gates; nonlinear equations; MCML gate; MOS current mode logic gates; bias current; energy-delay product; maximum area; maximum delay; nonlinear equations; power-delay product; quality metric; voltage swing; CMOS logic circuits; Crosstalk; Delay; Logic design; Logic gates; Nonlinear equations; Parasitic capacitance; Power dissipation; Voltage; Working environment noise;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465916
