Domain fault model and coverage metric for SoC verification

An innovative domain fault and coverage metric for SoC verification is proposed. The domain fault model is based on a geometrical analysis of the domain boundary and takes advantage of the fact that points on or near the boundary are most sensitive to domain errors. The purpose of this paper is to present an efficient fault model and coverage metric for measuring the completeness and quality of verification approach. The domain coverage metric has been implemented using VPI (Verilog procedural interface) and has been applied to verification of SoC (system on chip) design. Our domain coverage tool works smoothly with the simulator and vector generator. The results showed that the domain fault model is accurate and efficient, the domain coverage metric is powerful at finding the potential control path boundary faults.