Deterministic and low power BIST based on scan slice overlapping

Author

Li, Ji ; Han, Yinhe ; Li, Xiaowei

Author_Institution

Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China

fYear

2005

fDate

23-26 May 2005

Firstpage

5670

Abstract

This paper presents a new deterministic pattern generation structure that can be used in conjunction with any LFSR reseeding scheme. The proposed scheme utilizes scan slice overlapping to reduce the number of specified bits and the number of transitions at the same time. Thus, it can significantly reduce test power and evens control signals. Experimental results indicate that the proposed method significantly reduces the switching activity by 80% and only needs relatively small test data storage.

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; logic testing; low-power electronics; LFSR reseeding scheme; deterministic BIST; deterministic pattern generation structure; linear feedback shift registers; low power BIST; scan slice overlapping; specified bit number reduction; test cube don´t care bits; test power reduction; test storage reduction; transition number reduction; Built-in self-test; Circuit testing; Computers; Content addressable storage; Decoding; Memory; Power dissipation; Signal generators; Test data compression; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465924

Filename

1465924