A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes

Author

Brea, V.M. ; Laiho, M. ; Vilari, D.L. ; Paasio, A. ; Cabello, D.

Author_Institution

Dept. of Electron. & Comput. Sci., Univ. de Santiago de Compostela, Spain

fYear

2005

fDate

23-26 May 2005

Firstpage

5798

Abstract

This paper introduces a CMOS on-chip implementation intended for pixel-level snakes (PLS). The resultant architecture follows the SIMD paradigm. The B/W processing is executed on a discrete-time cellular neural network (DTCNN) array with a one-quadrant (1Q) model. The gray-scale processing is also run locally on a dedicated hardware. Electrical simulations on a proof-of-concept chip with a resolution of 9×9 pixels in a 0.18 micrometre CMOS technology process (ST Microelectronics) give some estimation of the figures of merit expected with the future chip measurements.

Keywords

cellular neural nets; image processing; neural chips; neural net architecture; parallel architectures; 1Q model; B/W processing; DTCNN array; SIMD paradigm; ST Microelectronics; discrete-time cellular neural network; gray-scale processing; neural network CMOS chip; one-quadrant cellular neural network; pixel-level snakes; CMOS technology; Cellular neural networks; Circuits; Data mining; Filling; Gray-scale; Hardware; Iterative algorithms; Layout; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465956

Filename

1465956