A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes

This paper introduces a CMOS on-chip implementation intended for pixel-level snakes (PLS). The resultant architecture follows the SIMD paradigm. The B/W processing is executed on a discrete-time cellular neural network (DTCNN) array with a one-quadrant (1Q) model. The gray-scale processing is also run locally on a dedicated hardware. Electrical simulations on a proof-of-concept chip with a resolution of 9×9 pixels in a 0.18 micrometre CMOS technology process (ST Microelectronics) give some estimation of the figures of merit expected with the future chip measurements.