Implementation of SIMD vision chip with 128×128 array of analogue processing elements

Author

Dudek, Piotr

Author_Institution

Sch. of Electr. & Electron. Eng., Manchester Univ., UK

fYear

2005

fDate

23-26 May 2005

Firstpage

5806

Abstract

This paper presents the latest implementation of the SIMD current-mode analogue matrix processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35 micrometre CMOS technology and comprises a 128×128 general-purpose programmable processor-per-pixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the analogue processing element is discussed and the design of control-signal drivers and readout circuitry is overviewed.

Keywords

CMOS image sensors; analogue processing circuits; array signal processing; computer vision; current-mode circuits; digital signal processing chips; parallel architectures; readout electronics; CMOS technology; SCAMP-3 vision chip; SIMD vision chip; analogue processing element array; analogue register; control-signal drivers; current-mode analogue matrix processor architecture; general-purpose programmable processor-per-pixel array; readout circuitry; CMOS technology; Computer vision; Driver circuits; Energy consumption; Image processing; Image sensors; Pixel; Process design; Registers; Sensor arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465958

Filename

1465958