The improvement for transaction level verification functional coverage

For hardware design, simulation is still the primary approach for functional verification of circuit descriptions written in hardware design language. The coverage metrics measure the process of validation and indicate the unexplored parts of the design. The paper describes a coverage-directed method that is suitable for transaction level verification. The approach is based on random test generation, and the coverage is increased by using a fault insertion method. Using case studies, we show how to establish the testbed and how this approach has been used to improve the quality of transaction level functional verification.