Approach for physical design in sub-100 nm era

In sub-100 nm processes, various physical phenomena come up as critical red-brick in designing circuits and LSIs. We focus on design for variability (DFV) for LSI-chip design, taking within-die variations into consideration. The main approach for the purpose is a new test structure, TEG (test element group), to measure the within-die variation of elements (MOS, R, C) and ring-oscillators. The precise measurement has been achieved with careful TEG design, including on-chip circuit, such as CBCM, Kelvin pattern. Reliable measurement data were analyzed statistically. Variation-caused systematic and random physical sources have been successfully decomposed with a newly developed extraction strategy. The data exhibits an extremely large variation in N/PMOS drain current (I_ds) and threshold voltage (V_th). The main sources of the random variation are doping fluctuation and line edge roughness (LER) in small size MOS transistors. I_ds variation is affected by the doping fluctuation. On the other hand, V_th variation is sensitive to LER. Interconnect variation is essentially small compared with the I_ds/V_th variation of MOS transistors; however, its variation is systematic component dominant. Ring oscillator T_pd variation is found to be closely related to I_ds variation, showing a correlation coefficient of 0.9. Design for variability is one of the most difficult challenges in 65-90 nm processes. Statistical design in the early stages will be necessary.