A 1.8 V 3.2 μW comparator for use in a CMOS imager column-level single-slope ADC

In this paper, a 1.8 V 3.2 μW comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 μV. The comparator is designed in a 0.18 μm CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.