Title :
A low power pipelined analog-to-digital converter using series sampling capacitors
Author :
Cho, SeongHwan ; Ock, Sungmin ; Lee, Sang-Hoon ; Lee, Joon-Suk
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea
Abstract :
A low power pipelined analog-to-digital converter (ADC) that employs sampling capacitors connected in series is presented. The series sampling capacitors minimize the size of the sampling capacitors to the kT/C limit without degrading the ADC´s performance due to mismatch. Using this technique, a 10-bit 100 MHz pipelined ADC is designed and simulated. The ADC achieves 60 dB of signal-to-noise-and-distortion ratio (SNDR) at 100 MHz while consuming 47 mW from 1.8-V supply in 0.18 μm CMOS technology.
Keywords :
CMOS integrated circuits; analogue-digital conversion; capacitors; integrated circuit noise; low-power electronics; pipeline processing; 0.18 micron; 1.8 V; 10 bit; 100 MHz; 47 mW; ADC; CMOS technology; kT/C limit; low power analog-to-digital converter; pipelined analog-to-digital converter; series sampling capacitors; Analog integrated circuits; Analog-digital conversion; CMOS process; CMOS technology; Capacitance; Capacitors; Degradation; Energy consumption; Linearity; Sampling methods;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1466051
